In order to manage data stored in a flash memory, a table, known as a logical-to-physical address map, is used to map logical block addresses (LBAs) to physical addresses in the memory. As memory capacity increases and as the reading resolution becomes finer, logical-to-physical address maps may grow larger. In some cases, the resolution of the addresses remains the same (e.g., 4 KB) even as the memory capacity increases. In some cases, it may be possible to read the memory in a finer resolution (e.g., 1 KB). In some cases, both memory capacity increases and finer resolution are implemented. In all of these cases, the size of the logical-to-physical address map grows larger and larger.
As the size of the logical-to-physical address map grows larger, it can become impractical to store the logical-to-physical address map in RAM. Therefore, large portions of the logical-to-physical address map are stored in the flash memory, and relevant portions of the map are transferred from the flash into the RAM as requested flash controller as part of flash management. Reading from the flash memory is time consuming. Therefore, it is desired to define the logical-to-physical address maps for minimizing delay in locating the physical address associated with a given logical address.
Some storage modules use a compression engine to compress data before storing it in memory. If the compression is implemented between the logical space and the physical space (i.e., the LBAs are not compressed, but data stored in the flash is), then several LBAs are stored in a memory area. Larger or additional logical-to-physical address maps can be used to address this situation. However, using larger or additional logical-to-physical address maps can add complexity and delay to the system.